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Book Cover
E-book
Author Sengupta, Anirban

Title Secured Hardware Accelerators for DSP and Image Processing Applications
Published Stevenage : Institution of Engineering & Technology, 2021
Online access available from:
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Description 1 online resource (405 pages)
Series Materials, Circuits and Devices Ser
Contents Intro -- Contents -- Preface -- Acknowledgements -- About the author -- List of acronyms -- List of notations -- 1. Introduction: secured and optimized hardware accelerators for DSP and image processing applications | Anirban Sengupta -- 1.1 Hardware accelerators: an introduction, definition, significance and applications -- 1.2 Role of ESL synthesis in hardware accelerator design -- 1.3 Hardware accelerators for popular DSP and image processing applications -- 1.4 Security techniques/algorithms/modules for securing hardware accelerators
1.5 A new paradigm in future ahead for EDA/VLSI/CE communities -- 1.6 Conclusion -- 1.7 Questions and exercise -- References -- 2. Cryptography-driven IP steganography for DSP hardware accelerators | Anirban Sengupta -- 2.1 Introduction -- 2.2 Contemporary approaches for securing hardware accelerators -- 2.3 Crypto-based steganography for securing hardware accelerators -- 2.4 Crypto-stego tool for securing hardware accelerators -- 2.5 Case studies on DSP hardware accelerator applications -- 2.6 Conclusion -- 2.7 Questions and exercise -- References
3. Double line of defence to secure JPEG codec hardware for medical imaging systems | Anirban Sengupta -- 3.1 Introduction -- 3.2 Why secure JPEG codec processors used in medical imaging systems? -- 3.3 Salient features of the chapter -- 3.4 Securing JPEG compression hardware using a double line of defence -- 3.5 Process of securing JPEG compression processor using double line of defence -- 3.6 Analysis on case studies -- 3.7 Conclusion -- 3.8 Questions and exercise -- References
4. Integrating multi-key-based structural obfuscation and low-level watermarking for double line of defence of DSP hardware accelerators | Anirban Sengupta -- 4.1 Introduction -- 4.2 Salient features of the chapter -- 4.3 Some practical applications of DSP hardware accelerators for modern electronic systems -- 4.4 Overview of contemporary approaches -- 4.5 Double line of defence using structural obfuscation and physical-level watermarking -- 4.6 Low-cost optimized multi-key-based structural obfuscation
4.7 Structural obfuscation and physical-level watermarking tool for securing hardware accelerators -- 4.8 Analysis of case studies -- 4.9 Conclusion -- 4.10 Questions and exercise -- References -- 5. Multimodal hardware accelerators for image processing filters | Anirban Sengupta -- 5.1 Introduction -- why dedicated image processing filter hardware is needed? -- 5.2 Why secure image processing filter hardware accelerators? -- 5.3 Salient features of the chapter -- 5.4 Selected contemporary approaches -- 5.5 Theory of 3 x 3 filter hardware accelerator
Notes Description based upon print version of record
5.6 Designing functionally reconfigurable obfuscated (secured) 3 x 3 filter hardware accelerator
Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators explored
Subject Image processing
Imaging systems in medicine
Particle accelerators
Cryptography
Public key cryptography
Form Electronic book
ISBN 9781839533075
1839533072
9781839533068