Title Hardware architectures for post-quantum digital signature schemes / Deepraj Soni, Kanad Basu, Mohammed Nabeel, Najwa Aaraj, Marc Manzano, Ramesh Karri

Published Cham : Springer, 2021

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Description 1 online resource Contents Introduction -- qTESLA -- CRYSTALS -Dilithium -- MQDSS -- SPHINCS -- Luov -- Falcon -- Picnic -- GeMSS -- Power, Performance, Area, and Security (PPAS) Comparison of the PQC Algorithms -- Conclusions Summary This book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels Bibliography Includes bibliographical references and index Subject Cryptography. Computer algorithms. Quantum computing. C (Computer program language) Computer engineering. Internet of things. Embedded computer systems. Microprocessors. Algorithms algorithms. C (Computer program language) Computer algorithms Computer engineering Cryptography Embedded computer systems Internet of things Microprocessors Quantum computing Form Electronic book Author Basu, Kanad, author Nabeel, Mohammed, author Aaraj, Najwa, 1983- author. Manzano, Marc, author Karri, Ramesh, author. ISBN 9783030576820 3030576825

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