| Description |
1 online resource (vii, 125 pages) : illustrations |
| Contents |
Cover -- Table of Contents -- Preface -- Chapter 1 Introduction -- 1.1 Motivation: Standard Cells vs. Transistors -- 1.2 Our Goals -- 1.3 Previous Transistor-Level Approaches -- 1.4 Overall Strategy -- 1.5 Book Outline -- Chapter 2 Circuit Structure And Clustering -- 2.1 Introduction -- 2.2 Trails -- 2.3 Essential Clusters and Circuit Structure -- 2.4 Pattern Matching -- 2.5 Circuit Structure Library -- 2.6 Benchmarks, Clustering Experiments and Results -- 2.7 Summary -- Chapter 3 Global Placement -- 3.1 Introduction -- 3.2 Quadratic Placement and Partitioning -- 3.3 Simulated Annealing Legalization -- 3.4 Global Placement Results -- 3.5 Summary -- Chapter 4 Detailed Placement And Layout Results -- 4.1 Introduction -- 4.2 Intra-Cluster Optimizations -- 4.3 Inter-Cluster Optimizations -- 4.4 Global Routability -- 4.5 Local Placement Optimization -- 4.6 Routing Integration -- 4.7 Layout Results -- 4.8 Summary -- Chapter 5 Timing-Driven Placement -- 5.1 Introduction -- 5.2 Transistor-Level Timing Analysis -- 5.3 Delay Graphs and Critical Paths -- 5.4 Timing-Driven Global Placement -- 5.5 Timing Results -- 5.6 Summary -- Chapter 6 Conclusion -- Appendix -- Bibliography |
| Summary |
"This book proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accomodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability." "The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout." "This book is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers."--Jacket |
| Bibliography |
Includes bibliographical references (pages 115-121) and index |
| Subject |
Digital integrated circuits.
|
|
Integrated circuit layout.
|
|
Transistor circuits.
|
| Form |
Electronic book
|
| Author |
Rutenbar, Rob A., 1957-
|
| LC no. |
2004051574 |
| ISBN |
1402076657 |
|
1402080638 (Ebook) |
|
6610147671 |
|
9781402076657 |
|
9781402080630 (Ebook) |
|
9786610147670 |
|
