| Description |
1 online resource (xii, 251 pages) : illustrations |
| Contents |
Preface; Analog Layout Area Optimization; Introduction; Experimental Activity; Introduction; Automatic placement tools in ST Microelectronics; Software for areas evaluation; Conclusions; References; Analysis of a Flash Memory Device; Introduction; The Flash Memory Cell; CMOS memories; The MOSFET with a floating gate; Comparison between Flash EPROM and EEPROM memories; Programming and erasing mechanisms; Simulation and Verification Flow; The simulation tool: Powermill; Simulation flow and verification; Electrical and Functional Characteristics of the Device; General Characteristics |
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Detailed description of signals. Bus operations; Command Interface; Read Operation; The Finite State Machine; Blocks Structure of the Device; Decoding; Pre-decoding and decoding of a column; The Read Path; Sense Amplifier; Program Operation; Instructions definition; Programming; The CUI; The internal microprocessor; The program algorithm; Device simulation; Erase Operation; Starting of the CUI state machine; The erase algorithm; Conclusions; References; VHDL Design, DFT, ATPG & Layout Implementation Service of a Digital Block for a DAC Converter; Introduction; Obtained Results |
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VHDL Design, DFT & Layout Implementation Service ProjectVHDL Design of DB-DAC Module; Some words about VHDL & synthesis; DAC block description; Convolution algorithm implementation; ROM & RAM mappings; Our architecture of the OVERSAMPLER module; -RAM & ROM memory; -Address generator; -Pre-accumulator; -MAC (Multiplier and Accumulator); -Selector; -Sequencer; -Control Logic; DFT Implementation and ATPG of DB-DAC; Testing of integrated circuits; Fault models; Test pattern; Fault and test coverage; Automatic test patterns generation (ATPG); Design for testability; Scan-path methodology |
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DFT Implementation flow for DB-DA CDFT Implementation and ATPG of DB-DAC; Scan chain insertion for DB-DAC; Test logic insertion for DB-DAC; Test pattern generation for DB-DAC; Chip Assembly and Layout Implementation; LVS results; Conclusions; References; Improving the ST20C2P Microprocessor: An Introduction; Introduction; The ST20 Microprocessor; Top level; Instruction representation; Instruction encoding; The instruction data value and prefixing; Primary Instruction; Secondary instructions; Grouping; C2P Pipeline Description; Improvement; IBuffer; Conclusions; References |
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Actual Status and Possible Development for CHIMERA Readout and Control SystemIntroduction; The Detectors; The Cs(Tl) crystal; Detector diagnostic; The Electronic Chain; The acquisition system; The Trigger System; The timing circuit; Conclusions; References; Passive Component Modelling with HFSS; Introduction; HFSS-Electromagnetic Simulator Ansoft; Finite Element Method (FEM); Design Flow with HFSS; Draw; Setup Materials; Setup Boundaries / Source; Setup Solution; Post-Processor; HSB2 Technology; Application and Results; Microstrips in metal 3; Microstrip design with HFSS; Results; Conclusions |
| Summary |
This volume covers a wide area - from research topics to the design and improvement of integrated circuit devices, already existing or to be introduced to the market |
| Bibliography |
Includes bibliographical references |
| Notes |
Print version record |
| Subject |
Microelectronics.
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System design.
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microelectronics.
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TECHNOLOGY & ENGINEERING -- Electronics -- Digital.
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TECHNOLOGY & ENGINEERING -- Electronics -- Microelectronics.
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Microelectronics
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System design
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MICROELECTRONICS.
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SYSTEMS ENGINEERING.
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ELECTRONICS.
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| Form |
Electronic book
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| Author |
Ferla, Giuseppe
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Fortuna, L. (Luigi), 1953-
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Imbruglia, Antonio
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| ISBN |
9789812792112 |
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9812792112 |
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