Description |
1 online resource (xxiv, 710 pages) : illustrations |
Series |
Springer series in advanced microelectronics, 1437-0387 ; 16 |
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Springer series in advanced microelectronics ; 16. 1437-0387
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Contents |
Cover -- Table of Contents -- Preface -- 1 The Economic Implications of Moore's Law -- 1.1 Introduction -- 1.2 Moore's Law: A Description -- 1.3 The History of Moore's Law -- 1.4 The Microeconomics of Moore's Law -- 1.5 The Macroeconomics of Moore's Law -- 1.6 Moore's Law Meets Moore's Wall: What is Likely to Happen. -- 1.7 Conclusion -- 1.8 Appendix A -- References -- Part I Classical Regime for SiO2 -- 2 Brief Notes on the History of Gate Dielectrics in MOS Devices -- 2.1 Early Attempts to Make Insulating-Gate Field-Effect Transistors; Surface States -- 2.2 Passivation of Silicon Surfaces by Thermal Oxidation; Planar Transistor Technology -- 2.3 Positive Oxide Charge and Surface States at the Si ... SiO2 Interface -- 2.4 Instabilities Due to Ion Drift Effects -- 2.5 Phosphate-silicate Glass Helped -- 2.6 Other Materials Tried as Gate-Dielectric Layers -- 2.7 Thermal Oxidation of Silicon -- 2.8 Segregation of Dopants at the Si ... SiO2 Int -- 2.9 Other Silicon Oxide Preparation Techniques -- 2.10 Thick Field Oxides -- 2.11 Breakdown Strength of SiO2, Defect Density, Moore's Law -- 2.12 Weak Oxide Regions in MOS Structures, Kooi Effect -- 2.13 Al Gate MOS Devices; PMOS IC's -- 2.14 Silicon Gate MOS Devices, NMOS and CMOS IC's -- 2.15 Decrease of Oxide Thickness Connected with Downscaling of MOS Structure -- References -- 3 SiO2 Based MOSFETS: Film Growth and Si ... SiO2 Interface Properties -- 3.1 SiO2 Prior to 1970 -- 3.2 After 1970: Progress in Understanding -- 3.3 Modern Era: The Quest for Thinner SiO2 and Alternatives -- References -- 4 Oxide Reliability Issues -- 4.1 Thin Oxide Layer Degradation Under Electrical Stress -- 4.2 Oxide Breakdown -- 4.3 Breakdown Acceleration Models -- 4.4 Conclusion -- References -- Part II Transition to Silicon Oxynitrides -- 5 Gate Dielectric Scaling to 2.0 ... 1.0 nm: SiO2 and Silicon Oxynitride -- 5.1 Device Requirements on Gate Dielectric Scaling -- 5.2 Definition of Gate Dielectric Thickness -- 5.3 Tunneling Current of SiO2 -- 5.4 Tunneling Currents of Silicon Oxynitride -- 5.5 Application Dependence of Gate Dielectric Limit -- References -- 6 Optimal Scaling Methodologies and Transistor Performance -- 6.1 Introduction -- 6.2 Scaling and Device Physics -- 6.3 Limitations of Conventional Scaling -- 6.4 Extending Validity of Moore's Law -- 6.5 Conclusions -- References -- 7 Silicon Oxynitride Gate Dielectric for Reducing Gate Leakage and Boron Penetration Prior to High-k Gate Dielectric Implementation -- 7.1 Introduction -- 7.2 Integrated RTCVD Oxynitride (ION) Process -- 7.3 JVD Nitride -- 7.4 DPN Oxynitride -- 7.5 Conclusion -- References -- Part III Transition to High-k Gate Dielectrics -- 8 Alternative Dielectrics for Silicon-Based Transistors: Selection Via Multiple Criteria -- 8.1 Introduction -- 8.2 Discussion -- 8.3 Conclusions. -- References -- 9 Materials Issues for High-k Gate Dielectric Selection and Integration -- 9.1 Introduction -- 9.2 MIS (Metal-Insulator-Semiconductor) Structures -- 9.3 Materials Properties and Integration Considerations -- 9.4 Conclusions -- References -- 10 Designing Interface Composition and Structure in High Dielectric Constant Gate |
Summary |
Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology. Topics include: an extensive review of Moore's Law, the classical regime for SiO2 gate dielectrics; the transition to silicon oxynitride gate dielectrics; the transition to high-K gate dielectrics (including the drive towards equivalent oxide thickness in the single-digit nanometer regime); and future directions and issues for ultimate technology generation scaling. The vision, wisdom, and experience of the team of authors will make this book a timely, relevant, and interesting, resource focusing on fundamentals of the 45 nm Technology Generation and beyond |
Analysis |
chemie |
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chemistry |
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condenseren |
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condensation |
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optische instrumenten |
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optical instruments |
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fysica |
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physics |
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engineering |
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oppervlakten |
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surfaces |
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grensvlak |
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interface |
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optica |
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optics |
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Chemistry (General) |
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Chemie (algemeen) |
Bibliography |
Includes bibliographical references and index |
Notes |
English |
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Print version record |
In |
Springer e-books |
Subject |
Integrated circuits -- Very large scale integration -- Materials
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Semiconductors -- Materials
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Metal oxide semiconductor field-effect transistors -- Materials
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Gate array circuits -- Materials -- Congresses
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Dielectrics.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated.
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
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Semiconductors -- Materials.
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Metal oxide semiconductor field-effect transistors -- Materials.
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Gate array circuits -- Materials.
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Dielectrics.
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Integrated circuits -- Very large scale integration -- Materials.
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Chimie.
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Science des matériaux.
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Dielectrics
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Gate array circuits -- Materials
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Integrated circuits -- Very large scale integration -- Materials
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Semiconductors -- Materials
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Genre/Form |
proceedings (reports)
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Conference papers and proceedings
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Conference papers and proceedings.
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Actes de congrès.
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Form |
Electronic book
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Author |
Huff, Howard R
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Gilmer, D. C. (David C.)
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LC no. |
2004105869 |
ISBN |
9783540264620 |
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3540264620 |
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3540210814 |
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9783540210818 |
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6610304750 |
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9786610304752 |
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