Introduction -- Definitions and Basic Properties -- Synthesis of FSMs -- State Assignment Algorithms -- Area Optimization Based on Graphs of Outputs -- Speed Optimization Using Tri-state Output Buffers -- Complex Strategies for FSMs -- Experiments -- Conclusions
Summary
This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures
