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E-book
Author Moiseev, Konstantin, author

Title Multi-net optimization of VLSI interconnect / Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Published New York, NY : Springer, [2014]
©2015

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Description 1 online resource (xvi, 233 pages) : illustrations (some color)
Contents Preface; Contents; About the Authors; Chapter 1: An Overview of the VLSI Interconnect Problem; 1.1 Driving Forces: Economy and Technology; 1.2 Complexity and Connectivity: A System Architect℗þs View; 1.3 Complexity and Connectivity: A Process Technologist℗þs View; 1.4 The Interconnect Scaling Problem; 1.5 Implications of the Interconnect Scaling Problem; 1.6 The Value of Multi-net Optimization; Chapter 2: Interconnect Aspects in Design Methodology and EDA Tools; 2.1 Interconnect Planning; 2.2 Interconnect Synthesis; 2.3 Final Generation of Interconnect Layout
2.4 Future Requirements for Interconnect SynthesisChapter 3: Scaling Dependent Electrical Modeling of Interconnects; 3.1 Technology Scaling; 3.1.1 Scaling of Transistors; 3.1.2 Scaling of Interconnects; 3.2 Circuit Models of Interconnect; 3.2.1 Ideal Interconnect; 3.2.2 Capacitive Interconnect; 3.2.3 Resistive Interconnect; 3.2.4 Resistive Interconnect Trees; 3.3 Scaling Effects on Interconnect Delay; 3.4 Cross-Capacitances and Their Decoupling with Miller Factor; 3.5 Interconnect Power; 3.6 Interconnect Noise (Crosstalk); Chapter 4: Frameworks for Interconnect Optimization
4.1 Net-by-Net Optimization4.2 Multi-net Optimizations; 4.2.1 Bundle of Wires; 4.2.2 General Wire Layouts with a Preferred Direction; 4.2.3 Optimization by Wire Ordering; 4.2.4 Interconnect Optimization in Automated Layout Migration; 4.2.5 Summary of Interconnect Optimization Frameworks; Chapter 5: Net-by-Net Wire Optimization; 5.1 Single-Stage Point-to-Point Wires; 5.1.1 Stage Delay with Capacitive Wire (Negligible Wire Resistivity); 5.1.2 Stage Delay with Resistive Wire; 5.1.3 Repeater Insertion; 5.1.4 Wire Sizing (Tapering); 5.2 Multistage Logic Paths; 5.2.1 Logical Effort Optimization
5.2.2 Logic Gates as Repeaters5.2.3 Unified Logical Effort -- Combined Optimization of Gates and Wires; 5.3 Tree-Structured Nets; Chapter 6: Multi-net Sizing and Spacing of Bundle Wires; 6.1 The Interconnect Bundle Model; 6.2 Power, Delay and Noise Metrics for a Bundle of Parallel Wires; 6.2.1 Calculating Parameters of Effective Driver and Effective Load; 6.2.2 The Role of Cross-Capacitance in Delay and Power Calculations for a Bundle of Parallel Wires; 6.2.2.1 Delay in a Bundle of Parallel Wires Using Miller Factor; 6.2.2.2 Power in a Bundle of Parallel Wires
6.2.3 Power and Delay Objectives for Optimizing a Bundle of Wires6.3 Bundle Spacing and Sizing with Continuous Design Rules; 6.3.1 Optimizing the Total Power of a Wire Bundle; 6.3.2 Optimizing the Total Sum (or Average) of Delays (Slacks); 6.3.3 Minimizing Maximal Delays and Negative Slack: MinMax Problems; 6.3.4 Iterative Algorithm for MinMax Delay or Slack; 6.3.5 The Relation Between the Minimal Total Sum and MinMax Solutions; 6.3.5.1 Examples; 6.4 Bundle Spacing and Sizing with Discrete Design Rules; 6.4.1 Introduction to Discrete Design Rules Problems
Summary This book examines design and migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects, covering scaling-dependent models for interconnect power, interconnect delay and crosstalk noise, plus design optimization problems
Analysis engineering
circuits
procesarchitectuur
process architecture
elektronica
electronics
instrumentatie
instrumentation
Engineering (General)
Techniek (algemeen)
Bibliography Includes bibliographical references and index
Notes Online resource; title from PDF title page (SpringerLink, viewed December 3, 2014)
Subject Interconnects (Integrated circuit technology)
Integrated circuits -- Very large scale integration.
Electronics engineering.
Computer architecture & logic design.
Circuits & components.
TECHNOLOGY & ENGINEERING -- Mechanical.
Integrated circuits -- Very large scale integration
Interconnects (Integrated circuit technology)
Form Electronic book
Author Kolodny, Avinoam, author
Wimer, Shmuel, author
ISBN 9781461408215
1461408210
1461408202
9781461408208