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E-book

Title Design and test technology for dependable systems-on-chip / Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors
Published Hershey, PA : Information Science Reference, ©2010

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Description 1 online resource (xxvi, 550 pages) : illustrations
Contents Section 1. Design, modeling, and verification -- section 2. Faults, compensation and repair -- section 3. Fault simulation and fault injection -- section 4. Test technology for systems-on-chip -- section 5. Test planning, compression and compaction in SoC's
Summary "This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"-- Provided by publisher
Bibliography Includes bibliographical references and index
Notes English
Print version record
Subject Systems on a chip -- Design and construction
Networks on a chip -- Design and construction
Systems on a chip -- Testing
Networks on a chip -- Testing
TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- Integrated.
TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
Systems on a chip -- Design and construction.
Form Electronic book
Author Ubar, Raimund, 1941-
Raik, Jaan, 1972-
Vierhaus, Heinrich Theodor, 1951-
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