Deakin University / All Locations

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Authors (Last name first) (1-3 of 3)
Thornton, Mitchell Aaron.
1 2010 Digital system verification : a combined formal methods and simulation framework Li, Lun, 1970- Rating: Electronic Resources
2 2006 Introduction to logic synthesis using Verilog HDL Reese, Robert B. (Robert Bryan), 1958- 1st ed Rating: Electronic Resources
3 2008 Multiple valued logic : concepts and representations Miller, D. Michael. Rating: Electronic Resources
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Digital system verification : a combined formal methods and simulation framework