| Description |
1 online resource (xvii, 166 pages) |
| Series |
Springer series in advanced microelectronics, 1437-0387 ; 34 |
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Springer series in advanced microelectronics ; 34.
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| Contents |
Adiabatic Logic; Preface; Acknowledgements; Contents; Abbreviations; Chapter 1: Introduction; 1.1 Motivation for this Work; 1.2 A Brief History of Reversible Computation and Adiabatic Logic; Chapter 2: Fundamentals of Adiabatic Logic; 2.1 The Charging Process in Adiabatic Logic Compared to Static CMOS; 2.1.1 The De?nition of the Energy Saving Factor (ESF); 2.2 An Adiabatic System; 2.2.1 Introducing Adiabatic Logic Families Used in This Work; 2.2.2 The Four-Phase Power-Clock; 2.3 Loss Mechanisms in Adiabatic Logic; 2.3.1 Impact of Process Variations on the Losses in Adiabatic Logic |
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2.4 Voltage Scaling-A Comparison of Static CMOS and Adiabatic Logic2.5 Properties of Adiabatic Logic and Resultant Design Considerations; 2.5.1 Dual-Rail Encoded Signals; 2.5.2 Inherent Pipelining; 2.5.3 Delay Considerations in Adiabatic Logic; 2.5.4 The Power Supply Net in Adiabatic Logic: Crosstalk, iR-drop, Ldidt-drop, Electromigration; Crosstalk; iR-drop; Ldidt-drop; Electromigration; 2.6 General Simulation Setup; Chapter 3: Future Trend in Adiabatic Logic; 3.1 Scaling Trends for Sub 90 nm Transistors; Industrial 65 nm Low-Power (LP) Process; PTM 45 nm High-Performance (HP) Process |
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PTM 32 nm High-Performance (HP) ProcessPTM 22 nm High-Performance (HP) Process; PTM 16 nm High-Performance (HP) Process; Overview of Scaling Trend; 3.2 Adiabatic Logic with Novel Devices; 3.2.1 What Should an Ideal (Novel) Device for Adiabatic Logic Look Like?; The Device's On-resistance; The Device's Capacitance; Impact of Reducing On-resistance or/and Capacitance; Sensitivity of fopt to Changes in the On-resistance and Capacitance; 3.2.2 Adiabatic Logic with Carbon Nanotubes (CNT); 3.2.2.1 The Chirality of a CNT and the CNTFET; 3.2.2.2 Simulation Results |
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3.2.3 Adiabatic Logic with the Vertical Slit Field Effect Transistor (VESFET)3.2.3.1 Simulation Results; De?nition of the Investigated Energy Saving Factors; Simulation Results for an Inverter Circuit; Simulation Results for a NAND Circuit; Simulation Results for a Four-Input NAND (NAND4) Circuit; Simulation Results for an Inverter Circuit with a Fan-Out of Four (FO4); 3.3 (Negative) Bias Temperature Instability ((N)BTI) and Hot Carrier Injection (HCI) in Adiabatic Logic; 3.3.1 Impact of NBTI on the Energy Dissipation of Adiabatic Logic Circuits; 3.3.1.1 Simulation Results for PFAL and ECRL |
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3.3.2 Comparison of the Stress Due to the Permanent NBTI in Static CMOS and AL3.3.3 How Will Positive Bias Temperature Instability (PBTI) Impact Adiabatic Logic?; Chapter 4: Generation of the Power-Clock; 4.1 Introduction; 4.2 Topologies of Inductor-Based Power-Clock Generators; 4.3 Impact of Pattern-Induced Capacitive Variations on the Energy Dissipation of the Synchronized 2N2P LC-oscillator; 4.3.1 Impact of Pattern-Induced Variations on the Dissipation of a Discrete-Cosine Transformation (DCT) System; 4.4 Generation of the Synchronization Signals |
| Summary |
Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design |
| Analysis |
Physics |
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Logic design |
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Electronics |
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Systems engineering |
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Electronic Circuits and Devices |
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Electronics and Microelectronics, Instrumentation |
| Bibliography |
Includes bibliographical references and index |
| Notes |
English |
| Subject |
Logic design.
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Adiabatic invariants.
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TECHNOLOGY & ENGINEERING -- Mechanical.
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Ingénierie.
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Adiabatic invariants
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Logic design
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| Form |
Electronic book
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| ISBN |
9789400723450 |
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9400723458 |
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