Intro -- Preface -- Organization -- Contents -- Design Methods and Tools -- Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks -- 1 Introduction -- 2 Background -- 3 Gaussian Process with an Analytic Mean Function -- 4 Accelerator and Dataset -- 4.1 Accelerator's Architecture -- 4.2 Dataset -- 5 Evaluation -- 6 Conclusion and Future Work -- References -- Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design -- 1 Introduction -- 2 State of the Art -- 3 Methodology -- 4 Experimental Evaluation
4.1 Experimental Setup -- 4.2 Combinatorial Designs -- 4.3 Sequential Design -- 5 Conclusion -- References -- Optimising Operator Sets for Analytical Database Processing on FPGAs -- 1 Introduction -- 2 Related Work -- 3 Database Primitives -- 4 Optimisation Targets -- 4.1 Hardware Operator Granularity -- 4.2 Matching of Composed Operators -- 5 Results -- 5.1 Evaluation Setup -- 5.2 Optimisation Process -- 5.3 Discussion -- 6 Conclusion -- References -- Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems -- 1 Introduction -- 2 Technical Background
2.1 Basic Concepts on Reconfiguration -- 2.2 IMPRESS -- 2.3 ARTICo3 -- 3 Enhancing Productivity with Advanced Reconfiguration Features -- 4 Integrating IMPRESS in ARTICo3 -- 4.1 Modifications in ARTICo3 Design Flow -- 4.2 Run-Time Reconfiguration Management of Relocatable Bitstreams -- 5 Model-Based Design of Hardware Accelerators -- 6 Experimental Results -- 7 Conclusions -- References -- Chisel Usecase: Designing General Matrix Multiply for FPGA -- 1 Introduction -- 2 High Level Methodology -- 2.1 High Level Description -- 2.2 From Application to Architecture -- 3 Methodology Usecase
4 Results -- 4.1 Experimental Setup -- 4.2 Control of Generated Hardware -- 4.3 Architecture Exploration: Dimensioning the Application -- 4.4 Existing Solutions -- 4.5 Analysis and Contribution -- 5 Conclusion -- References -- Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks -- 1 Introduction -- 2 Related Work -- 3 Cycle-Accurate Debugging by RNN -- 3.1 Design Methodology -- 3.2 RNN Implementation -- 4 Obstacle Avoidance as Use Case -- 5 Results -- 5.1 Resource Utilization -- 5.2 Debugging Through RNNs -- 5.3 Training Dataset Requirement -- 6 Conclusions -- References
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs -- 1 Introduction -- 2 Background and Related Works -- 2.1 Internal Configuration Access Port and Internal Configuration Controller -- 2.2 Dynamically Reconfigurable Processing Module -- 2.3 SRAM-Based FPGAs Radiation Sensitivity and Evaluation Methodologies -- 3 Evaluation Framework -- 3.1 DRPM Setup -- 3.2 Fault Injection Platform -- 4 Experimental Results -- 4.1 SEUs Injection Campaign Results -- Avionic Environment -- 4.2 MBUs Injection Campaign Results -- Space Environment
Summary
This book constitutes the proceedings of the 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, held in Toledo, Spain, in April 2020. The 18 full papers and 11 poster presentations presented in this volume were carefully reviewed and selected from 40 submissions. The papers are organized in the following topical sections: design methods & tools; design space exploration & estimation techniques; high-level synthesis; architectures; applications
Bibliography
Includes bibliographical references and author index
