Ch. 1. Introduction -- ch. 2. Concept of floating body cell and its operational principle -- ch. 3. Signal of floating body cell -- ch. 4. 128 Mbit floating body RAM on silicon-on-insulator -- ch. 5. Scaling of floating body cell -- ch. 6. Cell array architecture and sense amplifier design -- ch. 7. Design practices of floating body random access memory -- ch. 8. Floating body cell development activities and future directions
Summary
DRAM together with NAND Flash is driving semiconductor technologies with wide spectrum of usage ranging from PC, mobile phone and digital home appliances to solid-state disk (SSD). However, the DRAM cell which consists of a data storage capacitor (1C) and a switching transistor (1T) is facing serious difficulty in shrinking the size of the capacitor whose capacitance needs to be kept almost constant (20̃30fF) throughout generations. The availability of a new DRAM cell which does not rely on an explicit capacitor for storing its data is more than ever awaited for further increasing the bit dens
