| Description |
1 online resource (454 pages) |
| Series |
River Publishers Series in Optics and Photonics |
|
River Publishers series in optics and photonics.
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| Contents |
Front Cover -- Half Title Page -- RIVER PUBLISHERS SERIES IN OPTICSAND PHOTONICS -- Title Page -- Photonic Interconnects for Computing Systems Understanding and Pushing Design Challenges -- Copyright Page -- Contents -- List of Contributors -- List of Figures -- List of Tables -- List of Abbreviations -- Introduction -- PART I: Design, Application and Implementation -- Chapter 1 -- Unified Inter- and Intra-chip Optical Interconnect Networks -- 1.1 Introduction -- 1.2 Related Work -- 1.3 Architecture Overview -- 1.4 Intra-chip Network Design -- 1.4.1 Data Channel Design -- 1.4.1.1 Optical network interface -- 1.4.1.2 Optical transceiver -- 1.4.1.3 Channel segmentation -- 1.4.2 Control Subsystem -- 1.4.2.1 Channel partition -- 1.4.2.2 Node agent design -- 1.5 Inter-chip Network Design -- 1.5.1 Inter-chip Data Channel -- 1.5.2 Control Subsystem -- 1.6 Evaluations -- 1.6.1 Node Agent Power and Area -- 1.6.2 Performance -- 1.6.3 Energy Efficiency -- 1.7 Conclusion -- References -- Chapter 2 -- Design and Optimization of Vertical Interconnections for Multilayer Optical Networks-on-Chip -- 2.1 Introduction -- 2.2 Materials for Photonic Integrated Circuit Fabrication -- 2.3 Technological Platforms for Multilayer Photonics -- 2.4 Overview of Vertical Interconnection Schemes -- 2.5 Isolation between Layers in Vertical Stacked Structures -- 2.6 Design Space Exploration of Inverse Tapered Couplers -- 2.7 Design of MMI-based Vertical Links -- 2.8 Concluding Remarks -- Acknowledgments -- References -- Chapter 3 -- Optical Interconnection Networks: The Need for Low-Latency Controllers -- 3.1 Introduction -- 3.2 Control Strategies -- 3.2.1 Time Sharing -- 3.2.2 Circuit-Switching -- 3.2.3 Wavelength Division -- 3.3 Low-Latency Controlling Solution for OINs -- 3.4 Results -- 3.5 State of the Art -- 3.6 Conclusion -- References |
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Chapter 4 -- Interconnects and Data System Throughput -- 4.1 Introduction -- 4.2 Interconnections -- 4.2.1 Electrical and Optical Interconnections -- 4.2.1.1 Electrical interconnections -- 4.2.1.2 Optical interconnections -- 4.3 Photonic Transceivers -- 4.4 Data Centers -- 4.4.1 Energy Use -- 4.4.2 Folded Clos (Leaf-Spine) Architecture -- 4.4.3 Hierarchy of Interconnection -- 4.4.4 Electrical Switching -- 4.4.5 Electrical versus Optical -- 4.5 Modeling of Optically Connected Data Centers -- 4.5.1 Data Center Modeling -- 4.5.2 Optics in Data Center Simulation -- 4.6 Disaggregation -- 4.7 Discussion -- 4.8 Conclusion -- References -- PART II: Developing Design Automation Solutions and Enabling Design Exploration -- Chapter 5 -- Design Automation Beyond Its Electronic Roots: Toward a Synthesis Methodology for Wavelength-Routed Optical Networks-on-Chip -- 5.1 Introduction -- 5.2 Analogy with EDA Flows -- 5.3 Wavelength-Selective Routing -- 5.4 WRONoC Synthesis Methodology at a Glance -- 5.5 Front-End Synthesis Methodology -- 5.5.1 Wavelength Resolution -- 5.5.2 Technology Mapping -- 5.5.3 Symbolic Wavelength Assignment -- 5.5.4 Topology Connection -- 5.6 Device Parameter Selection -- 5.6.1 The Routing Fault Concern -- 5.6.2 The Role of Parameter Uncertainty -- 5.6.3 Problem Formulation: A Case Study -- 5.7 Physical Mapping Flow -- 5.8 Experimental Results -- 5.8.1 Synthesis of Logical Topologies -- 5.8.2 The Design Predictability Gap -- 5.8.3 Bounds on Connectivity and Parallelism -- 5.9 Conclusions -- References -- Chapter 6 -- Application-Specific Mapping Optimizations for Photonic Networks-on-Chip -- 6.1 Introduction -- 6.2 Motivation: Application-Specific Mapping Optimization -- 6.3 Architecture Description -- 6.3.1 Architecture Overview -- 6.3.2 The Photonic Switch Element Model -- 6.3.3 The Router Model -- 6.4 Methodology -- 6.4.1 Problem Formulation |
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6.4.2 Genetic Algorithm -- 6.5 Results -- 6.6 Conclusion -- References -- Chapter 7 -- Integrated Photonics for Chip-Multiprocessor Architectures -- 7.1 Introduction -- 7.2 Tiled Architectures and Networks on Chip -- 7.2.1 Limits of Electronic Wires and Benefits of Silicon Photonics from the Architectural Viewpoint -- 7.3 Coherence Protocols -- 7.4 Experimental Methodology -- 7.4.1 Simulator -- 7.4.2 Benchmarks -- 7.5 Passive Optical Networks for CMPs -- 7.5.1 Analyzed Architecture -- 7.5.2 Arbitration Strategies and Physical Layout Implications -- 7.5.3 Results -- 7.6 Optical Dynamic Reconfigurable Networks for CMPs -- 7.6.1 Background on Circuit Switched Optical NoCs -- 7.6.2 Limitations of Existing Solutions -- 7.6.3 Analyzed Architecture -- 7.6.3.1 Logical operating scheme -- 7.6.4 Results -- 7.7 Conclusions -- References -- PART III: Challenges in Performance Analysis and Design Solutions -- Chapter 8 -- Thermal Management of Silicon Photonic NoCs in Many-core Systems -- 8.1 Introduction -- 8.2 Thermal Sensitivity of Optical Devices in PNoCs -- 8.3 Design Methods for Thermal Management in PNoCs -- 8.3.1 Device-level Techniques -- 8.3.2 Chip-level Techniques -- 8.4 Runtime Methods for Thermal Management in PNoCs -- 8.5 Conclusion -- Acknowledgement -- References -- Chapter 9 -- Thermal-Aware Design Method for On-Chip Laser-based Optical Interconnect -- 9.1 Introduction -- 9.2 Related Work -- 9.3 3D Architecture -- 9.3.1 Architecture Overview -- 9.3.2 ONoC Interface and Thermal Sensitivity -- 9.3.3 CMOS-Compatible On-Chip Lasers -- 9.3.4 Contribution -- 9.4 Proposed Design Methodology -- 9.4.1 Design Methodology Overview -- 9.4.2 Thermal Analysis -- 9.4.3 SNR Analysis -- 9.4.3.1 SNR model -- 9.4.3.2 Signal attenuation and crosstalk -- 9.4.3.3 Transmission principles of MR -- 9.5 Case Study -- 9.5.1 System Specification -- 9.5.1.1 SCC and package |
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9.5.1.2 ORNoC -- 9.5.2 SNR Analysis in the Considered Architecture -- 9.5.3 Thermal Characteristics of On-Chip Laser -- 9.6 Results -- 9.6.1 Reduction of the ONI Gradient Temperature -- 9.6.2 System Level Estimation of SNR -- 9.7 Conclusion -- Acknowledgment -- References -- Chapter 10 -- Fault-tolerant Photonic Network-on-Chip -- 10.1 Introduction -- 10.1.1 Design Challenges -- 10.1.2 Fault Models -- 10.1.2.1 PNoC signal strength -- 10.1.2.2 Electrostatic discharge -- 10.1.2.3 Noise -- 10.1.2.4 Aging -- 10.1.2.5 Process variability -- 10.1.2.6 Temperature variation -- 10.2 Fault-tolerant Photonic Network-on-Chip Architecture -- 10.2.1 Microring Fault-resilient Photonic Router -- 10.2.2 Light-weight Electronic Control Router -- 10.2.3 Fault-tolerant Path-configuration and Routing -- 10.3 Evaluation -- 10.3.1 Complexity Evaluation -- 10.3.2 Latency and Bandwidth Evaluation -- 10.3.3 Energy Evaluation -- 10.4 Related Literature -- 10.5 Chapter Summary and Discussion -- References -- Chapter 11 -- Techniques for Energy Proportionality in Optical Interconnects -- 11.1 Laser Power-Gating -- 11.1.1 Why Lasers Waste Power -- 11.1.2 The Solution: Laser Power-Gating -- 11.1.3 Background -- 11.1.3.1 Laser primer -- 11.1.3.2 Nanophotonic interconnect topologies -- 11.1.4 Laser Control Schemes -- 11.1.4.1 Proactive laser control -- 11.1.4.2 Controlling an off-chip laser source -- 11.1.5 Experimental Methodology -- 11.1.5.1 Interconnect modeling -- 11.1.5.2 Modeling optical and electrical multicore NoC -- 11.1.5.3 Laser power modeling -- 11.1.5.4 Resonant ring heater modeling -- 11.1.5.5 The overheads of laser control -- 11.1.6 Experimental Results -- 11.1.7 Case Study 1: Radix-16 R-SWMR -- 11.1.8 Case Study 2: Firefly -- 11.1.9 Related Work -- 11.2 Minimizing Ring Trimming Power -- 11.2.1 Introduction -- 11.2.2 Solution: Photonic Die Insulation with Parka |
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11.2.3 Experimental Methodology -- 11.2.3.1 Modeling the Ring-Heater Power Consumption -- 11.2.3.2 Modeling cooling solutions -- 11.2.4 Experimental Results -- 11.2.4.1 Impact on ring-heating power consumption -- 11.2.4.2 Impact on a realistic multicore -- 11.2.5 Related Work -- 11.3 Future Work -- Acknowledgements -- References -- PART IV: On the Impact of Fabrication Non-Uniformity -- Chapter 12 -- Impact of Fabrication Non-Uniformity on Silicon Photonic Networks-on-Chip -- 12.1 Introduction -- 12.2 Optical Waveguides and MR-Based Devices -- 12.2.1 Strip Waveguides under Process Variations -- 12.2.2 MR-Based Add-Drop Filters and Switches under Process Variations -- 12.2.2.1 Resonant wavelength shift in MRs -- 12.2.3 Optical Spectra of MRs under Process Variations -- 12.3 Optical Networks-on-Chip under Process Variations -- 12.3.1 Process Variations in Optical Switches -- 12.3.2 Process Variations at the System-Level in ONoCs -- 12.4 Quantitative Simulation Results and Evaluations -- 12.4.1 Simulation Results at the Component- and Device-level -- 12.4.2 Simulation Results at the System-level -- 12.5 Chip Fabrication and Measurement Results -- 12.6 Conclusion -- References -- Chapter 13 -- Enhancing Process Variation Resilience in Photonic NoC Architectures -- 13.1 Introduction -- 13.2 Related Work -- 13.3 Analytical Model for PV-Aware Crosstalk Analysis -- 13.3.1 Impact of Localized Trimming on Crosstalk -- 13.3.2 Crosstalk Modeling for Corona PNoC -- 13.3.3 Modeling PV of MR Devices in Corona PNoC -- 13.4 Double-Bit Crosstalk Mitigation (DBCTM) -- 13.4.1 Overview -- 13.4.2 DBCTM Sensitivity Analysis with Corona PNoC -- 13.5 Experiments -- 13.5.1 Experimental setup -- 13.5.2 Experimental Results with Corona PNoC -- 13.6 Conclusion -- References -- Index -- About the Editors -- Back Cover |
| Notes |
Print version record |
| Subject |
Computer systems.
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|
Computer Systems
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Computer systems.
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| Form |
Electronic book
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| Author |
Nikdast, Mahdi
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Le Beux, Sébastien
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| ISBN |
9788793519794 |
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8793519796 |
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