| Description |
1 online resource (515 p.) |
| Contents |
Intro -- Preface -- Acknowledgments -- Contents -- About the Author -- 1 Flip Chip Technology -- 1.1 Introduction -- 1.2 Wafer Bumping-Stencil Printing -- 1.2.1 Sample Description and Experiment Setup -- 1.2.2 Taguchi Design of Experiments -- 1.2.3 Control Factors in Stencil Printing -- 1.2.4 Paste Printing and Reflow -- 1.2.5 Solder Volume -- 1.2.6 Data Analysis of the L8 Experiments -- 1.2.7 Data Analysis of the L4 Experiments -- 1.2.8 Summary -- 1.3 Wafer Bumping-Electroplating -- 1.3.1 C4 Bump -- 1.3.2 C2 Bump -- 1.3.3 C4 Bump versus C2 Bump -- 1.4 Flip Chip Package Substrate |
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1.5 Flip Chip Package Substrates-Organic -- 1.5.1 Printed Circuit Boards (PCBs) -- 1.5.2 Build-Up Package Substrates -- 1.5.3 Coreless Package Substrates -- 1.5.4 BOC and BOL Substrates -- 1.5.5 Embedded Trace Substrates (ETS) -- 1.5.6 Thin-Film Layers on Build-Up Package Substrates -- 1.6 Flip Chip Package Substrates-Fan-Out EMC/RDL -- 1.6.1 Fan-Out Chip-First RDL-Substrate -- 1.6.2 Fan-Out Chip-Last Hybrid Substrate -- 1.7 Flip Chip Package Substrates-TSV-Interposer -- 1.7.1 Passive TSV-Interposers -- 1.7.2 Active TSV-Interposers |
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1.8 Flip Chip Package Substrates-Si-Bridge Embedded in Organic Substrate -- 1.8.1 Intel's EMIB -- 1.8.2 IBM's DBHi -- 1.9 Flip Chip Package Substrates-Si-Bridge Embedded in Fan-Out EMC with RDLs -- 1.9.1 Unimicron's Si-Bridge -- 1.9.2 TSMC's CoWoS-L -- 1.9.3 SPIL's FO-EB-T -- 1.10 Flip Chip Assembly -- 1.10.1 Cu-to-Cu TCB Direct Bonding -- 1.10.2 Cu-to-Cu Room Temperature Direct (Hybrid) Bonding -- 1.10.3 C4 Solder Mass Reflow with CUF -- 1.10.4 C2 Solder Mass Reflow with CUF -- 1.10.5 TCB with Low-Bonding Force with CUF -- 1.10.6 C2 TCB with High-Bonding Force (NCP and NCF) |
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1.11 Underfill/Reliability -- 1.11.1 Post-Assembly Underfill -- 1.11.2 Pre-assembly Underfill -- 1.12 Reliability-Characterization of Underfill -- 1.12.1 Underfill Materials and Applications -- 1.12.2 Curing Conditions -- 1.12.3 Underfill Material Properties -- 1.12.4 Underfill Flow Rate -- 1.12.5 Mechanical Performance -- 1.12.6 Electrical Performance -- 1.12.7 Ranking of Underfill Encapsulants -- 1.12.8 Summary -- 1.13 Reliability-Stencil Printing of Underfill -- 1.13.1 New Stencil Design -- 1.13.2 Test Vehicles -- 1.13.3 Experiments -- 1.13.4 Characterizations -- 1.13.5 Summary |
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1.14 LPC-A High Throughput TCB Process -- 1.14.1 Experimental Procedure -- 1.14.2 Bonding Quality Evaluation -- 1.14.3 Stand-Off Height Control -- 1.14.4 Thermal Fatigue -- 1.14.5 Summary -- 1.15 Summary -- References -- 2 Cu-Cu Hybrid Bonding -- 2.1 Introduction -- 2.2 Samsung's Hybrid Bonding -- 2.3 SK Hynix's Hybrid Bonding -- 2.4 Micron's Hybrid Bonding -- 2.5 Mitsui's Hybrid Bonding -- 2.6 Sony's Hybrid Bonding -- 2.7 CEA-Leti's Hybrid Bonding -- 2.8 TEL's Hybrid Bonding -- 2.9 Applied Materials' Hybrid Bonding -- 2.10 Intel's Hybrid Bonding -- 2.11 TSMC's Bumpless Cu-Cu Bonding |
| Summary |
This book focuses on the design, materials, process, fabrication, and reliability of flip chip, hybrid bonding, fan-in, and fan-out technology. Both principles and engineering practice have been addressed, with more weight placed on engineering practice. This is achieved by providing in-depth study on a number of major topics such as wafer bumping, flip chip assembly, underfill and reliability, chip-to-wafer, wafer-to-wafer, Cu-Cu hybrid bonding, WLCSP, 6-side molded WLCSP, FOWLP such as hybrid substrates with PID, ABF, and ultra-large organic interposer, the communications between chiplets and heterogeneous integration packaging, and on-board optics, near-package optics, and co-packaged optics. The book benefits researchers, engineers, and graduate students in the fields of electrical engineering, mechanical engineering, materials sciences, industry engineering, etc |
| Notes |
2.12 MKS' Hybrid Bonding |
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Online resource; title from PDF title page (SpringerLink, viewed May 30, 2024) |
| Subject |
Interconnects (Integrated circuit technology)
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| Form |
Electronic book
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| ISBN |
9789819721405 |
|
9819721407 |
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