Title Creating assertion-based IP / Harry D. Foster, Adam C. Krolnik

Published New York ; London : Springer, 2007

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Description 1 online resource (1 volume) Series Series on integrated circuits and systems Series on integrated circuits and systems. Contents Front Matter; Introduction; Definitions and Terminology; The Process; Bus-Based Design Example; Interfaces; Arbiters; Controllers; Datapath; Back Matter Summary A project's functional verification testplan is the specification for the verification process. Developing this testplan involves the entire engineering team. This book discusses the process of testplanning using assertion languages (such as SystemVerilog assertions and PSL) to create verification IP which helps projects stay within their budget Analysis engineering circuits computertechnieken computer techniques computer software elektrotechniek electrical engineering Engineering (General) Techniek (algemeen) Bibliography Includes bibliographical references and index Notes Print version record In Springer e-books Subject Integrated circuits -- Verification. Ingénierie. Integrated circuits -- Verification Form Electronic book Author Krolnik, Adam C ISBN 9780387683980 0387683984

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