| Description |
1 online resource (xix, 187 pages) : illustrations |
| Series |
Springer Series in Advanced Microelectronics, 1437-0387 ; volume 47 |
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Springer series in advanced microelectronics ; v. 47. 1437-0387
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| Contents |
880-01 Degradation mechanisms -- Techniques and devices -- Negative Bias Temperature Instability in (Si)Ge pMOSFETs -- Negative Bias Temperature Instability in nanoscale devices -- Channel Hot Carriers and other reliability mechanisms -- Conclusions and perspectives |
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880-01/(S Machine generated contents note: 1. Introduction -- 1.1. CMOS Scaling: Evolutionary Era -- 1.2. CMOS Scaling: Revolutionary Era -- 1.2.1. Strain Engineering (90 and 65 nm Technology Nodes) -- 1.2.2. High-k Metal Gate Technology -- 1.2.3. Tri-Gate (finFET) Technology -- 1.3. High Mobility Channels for Future CMOS Technology Nodes -- 1.4. Reliability Limitations -- 1.5. Variability Issues -- 1.6. Objectives and Structure of this Work -- 1.7. Summary of this Chapter -- References -- 2. Degradation Mechanisms -- 2.1. Introduction -- 2.2. Negative Bias Temperature Instability -- 2.2.1. First-Order Phenomenological Observations -- 2.2.2. Basic Interpretation: Why does the Vth Shift-- 2.2.3. NBTI Relaxation -- 2.2.4. Reaction-Diffusion Model -- 2.2.5. NBTI Relaxation: A Crucial Benchmark for Degradation Models -- 2.2.6. Recent NBTI Observations: Small-Area Devices -- 2.2.7. Extended Shockley-Read-Hall Trapping Models -- 2.2.8. Nonradiative Multiphonon Theory -- 2.2.9. Defect Model for RTN and NBTI -- 2.2.10. Two-Stage Model for NBTI -- 2.3. Hot Carriers -- 2.3.1. Hot Carrier Typology -- 2.3.2. First-Order Modeling of Channel hot Carrier Generation -- 2.3.3. Hot Carrier Degradation -- 2.4. Time-Dependent Dielectric Breakdown -- 2.5. Summary of this Chapter -- References -- 3. Techniques and Devices -- 3.1. Introduction -- 3.2. Advanced NBTI Measurement Techniques -- 3.2.1. Measure-Stress-Measure Techniques -- 3.2.2. On-the-fly Measurement Techniques -- 3.3. Techniques and Methodologies used in this Work -- 3.3.1. eMSM Implementation -- 3.3.2. From eMSM Data to Lifetime Extrapolation and Benchmarking -- 3.3.3. Empirical Analytical Description of NBTI Relaxation Traces: Extraction of the So-Called ̀Recoverable' and ̀Permanent' Components -- 3.3.4. NBTI Experiments in Nanoscaled Devices -- 3.3.5. Charge Pumping Technique -- 3.4. Devices used in this Work -- 3.4.1. Ge Fraction -- 3.4.2. QW Thickness -- 3.4.3. Si Cap Thickness -- 3.5. Structures used in this Work -- 3.5.1. Standard SiGe Device Structures -- 3.5.2. Special Structures: Poly-Si Heaters -- 3.6. Summary of this Chapter -- References -- 4. Negative Bias Temperature Instability in (Si)Ge pMOSFETs -- 4.1. Introduction -- 4.2. Impact of the Individual Gate Stack Parameters -- 4.2.1. Ge Fraction -- 4.2.2. SiGe Quantum Well Thickness -- 4.2.3. Si Cap Thickness -- 4.3. Gate Stack Optimization: Demonstrating Sufficient NBTI Reliability at UT-EOT -- 4.4. Process- and Architecture-Independent Results -- 4.5. Detailed Discussion of the Experimental Results -- 4.5.1. Power-Law Time Exponent and Eox-Acceleration -- 4.5.2. Temperature Activation -- 4.5.3. Interface State Creation (ΔNit) and Hole Trapping (ΔNot) -- 4.5.4. Faster NBTI Relaxation -- 4.5.5. Summary of the Experimental Observations -- 4.6. Body Bias and NBTI -- 4.6.1. Body Bias During NBTI Stress Only -- 4.6.2. Body Bias During NBTI Stress and Relaxation -- 4.7. Model -- 4.7.1. Disqualified Models -- 4.7.2. Reduced P (ΔNit) -- 4.7.3. Reduced R (ΔNot)-A Model for the Superior NBTI Reliability of (Si)Ge Channel pMOSFETs -- 4.8. Final Considerations: Performance Versus Reliability -- 4.9. Summary of this Chapter -- References -- 5. Negative Bias Temperature Instability in Nanoscale Devices -- 5.1. Introduction -- 5.2. NBTI on Nanoscale SiGe Devices -- 5.2.1. Individual Discharge Events -- 5.2.2. Average Number of Active Defects per Device (NT) -- 5.2.3. Average AVth Impact per Charged Defect η -- 5.2.4. Average Charged Defect Emission Time -- 5.2.5. Summary of the Experimental Observations -- 5.3. Implications for the Time-Dependent Variability -- 5.4. Model -- 5.5. Impact of Single Charged Gate Oxide Defects: Area Scaling -- 5.6. Impact of Single Charged Gate Oxide Defects on the Entire FET Current Characteristics: VG-Dependence -- 5.6.1. Experimental Results -- 5.6.2. Discussion -- 5.7. Impact of Single Charged Gate Oxide Defects: Body Bias Dependence -- 5.8. Summary of this Chapter -- References -- 6. Channel Hot Carriers and Other Reliability Mechanisms -- 6.1. Introduction -- 6.2. Experimental Methodology for Studying the Interplay of CHC and NBTI -- 6.3. Interaction of CHC and NBTI in pMOSFETs -- 6.3.1. Recoverable Component -- 6.3.2. Permanent Component -- 6.3.3. Consequences for Si Channel Devices -- 6.3.4. Summary of this Section -- 6.4. CHC in SiGe pMOSFETs -- 6.4.1. Impact of the Si Cap Thickness -- 6.4.2. CHC Lifetime of the NBTI-Optimized SiGe Gate Stack -- 6.4.3. Summary of this Section -- 6.5. CHC in Ge pMOSFETs -- 6.5.1. Halo Engineering -- 6.5.2. Summary of this Section -- 6.6. Other Reliability Mechanisms -- 6.6.1. Low-Frequency Noise -- 6.6.2. Time-Dependent Dielectric Breakdown -- 6.7. Summary of this Chapter -- References -- 7. Conclusions and Perspectives -- 7.1. Conclusions -- 7.2. Perspectives |
| Summary |
Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and presented here show the reliability improvement to be process- and architecture-independent and, as such, readily transferable to advanced device architectures as Tri-Gate (finFET) devices. We propose a physical model to understand the intrinsically superior reliability of the MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack. The improved reliability properties here discussed strongly support (Si)Ge technology as a clear frontrunner for future CMOS technology nodes |
| Bibliography |
Includes bibliographical references |
| Notes |
Online resource; title from PDF title page (SpringerLink, viewed October 21, 2013) |
| Subject |
Metal oxide semiconductor field-effect transistors -- Reliability
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Metal oxide semiconductors, Complementary -- Reliability
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TECHNOLOGY & ENGINEERING -- Mechanical.
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Metal oxide semiconductors, Complementary -- Reliability
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| Form |
Electronic book
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| Author |
Kaczer, Ben, author
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Groeseneken, Guido, author
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| ISBN |
9789400776630 |
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9400776632 |
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