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Author Cruz, Eduardo H. M., author

Title Thread and data mapping for multicore systems : improving communication and memory accesses / Eduardo H.M. Cruz, Matthias Diener, Philippe O.A. Navaux
Published Cham, Switzerland : Springer, [2018]
©2018

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Description 1 online resource (ix, 54 pages) : illustrations
Series SpringerBriefs in computer science
SpringerBriefs in computer science.
Contents Intro; Preface; Contents; Acronyms; 1 Introduction; 1.1 Improving Memory Locality with Sharing-Aware Mapping; 1.2 Monitoring Memory Accesses for Sharing-Aware Mapping; 1.3 Organization of the Text; 2 Sharing-Aware Mapping and Parallel Architectures; 2.1 Understanding Memory Locality in Shared Memory Architectures; 2.1.1 Lower Latency When Sharing Data; 2.1.2 Reduction of the Impact of Cache Coherence Protocols; 2.1.3 Reduction of Cache Misses; 2.1.3.1 Capacity Misses; 2.1.3.2 Invalidation Misses; 2.1.3.3 Replication Misses; 2.1.4 Reduction of Memory Accesses to Remote NUMA Nodes
2.1.5 Better Usage of Interconnections2.2 Example of Shared Memory Architectures Affected by Memory Locality; 2.2.1 Intel Harpertown; 2.2.2 Intel Nehalem/Sandy Bridge; 2.2.3 AMD Abu Dhabi; 2.2.4 Intel Montecito/SGI NUMAlink; 2.3 Locality in the Context of Network Clusters and Grids; 3 Sharing-Aware Mapping and Parallel Applications; 3.1 Parallel Applications and Sharing-Aware Thread Mapping; 3.1.1 Considerations About the Sharing Pattern; 3.1.1.1 Dimension of the Sharing Pattern; 3.1.1.2 Granularity of the Sharing Pattern (Memory Block Size)
3.1.1.3 Data Structure Used to Store the Thread Sharers of a Memory Block3.1.1.4 History of the Sharing Pattern; 3.1.2 Sharing Patterns of Parallel Applications; 3.1.3 Varying the Granularity of the Sharing Pattern; 3.1.4 Varying the Number of Sharers of the Sharing Pattern; 3.2 Parallel Applications and Sharing-Aware Data Mapping; 3.2.1 Parameters that Influence Sharing-Aware Data Mapping; 3.2.1.1 Influence of the Memory Page Size; 3.2.1.2 Influence of Thread Mapping; 3.2.2 Analyzing the Data Mapping Potential of Parallel Applications
3.2.3 Influence of the Page Size on Sharing-Aware Data Mapping3.2.4 Influence of Thread Mapping on Sharing-Aware Data Mapping; 4 State-of-the-Art Sharing-Aware Mapping Methods; 4.1 Sharing-Aware Static Mapping; 4.1.1 Static Thread Mapping; 4.1.2 Static Data Mapping; 4.1.3 Combined Static Thread and Data Mapping; 4.2 Sharing-Aware Online Mapping; 4.2.1 Online Thread Mapping; 4.2.2 Online Data Mapping; 4.2.3 Combined Online Thread and Data Mapping; 4.3 Discussion on Sharing-Aware Mapping and the State-of-Art; 4.4 Improving Performance with Sharing-Aware Mapping; 4.4.1 Mapping Mechanisms
4.4.1.1 Source Code Changes4.4.1.2 Offline Profiling at the User Level; 4.4.1.3 Runtime Options; 4.4.1.4 Online Profiling at the System Level; 4.4.2 Methodology of the Experiments; 4.4.3 Results; 5 Conclusions; References
Summary This book presents a study on how thread and data mapping techniques can be used to improve the performance of multi-core architectures. It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures. On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access. Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified
Bibliography Includes bibliographical references
Notes Online resource; title from PDF title page (EBSCO, viewed July 12, 2018)
Subject Parallel programming (Computer science)
Multiprocessors.
Threads (Computer programs)
Digital mapping.
Software Engineering.
Computer hardware.
COMPUTERS -- Programming -- Parallel.
Digital mapping
Multiprocessors
Parallel programming (Computer science)
Threads (Computer programs)
Form Electronic book
Author Diener, Matthias
Navaux, Philippe O. A., author.
ISBN 9783319910741
3319910744