| Description |
1 online resource (xxi, 223 pages) : illustrations |
| Series |
Lecture notes in electrical engineering ; v. 45 |
|
Lecture notes in electrical engineering ; v. 45.
|
| Contents |
MICRO-Architectural Exploration -- A Baseline NoC Architecture -- ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39] -- RoCo: The Row-Column Decoupled Router -- A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40] -- Exploring FaultoTolerant Network-on-Chip Architectures [37] -- On the Effects of Process Variation in Network-on-Chip Architectures [45] -- MACRO-Architectural Exploration -- The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15] -- Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43] -- A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44] -- Digest of Additional NoC MACRO-Architectural Research -- Conclusions and Future Work |
| Summary |
NoC architectures are seen as a possible solution to burgeoning global wiring delays in many-core chips, and this work deals with the main issues that need to be resolved in performance, energy efficiency, reliability, variability and silicon area consumption |
| Bibliography |
Includes bibliographical references |
| Notes |
English |
|
Print version record |
| Subject |
Networks on a chip.
|
|
COMPUTERS -- Software Development & Engineering -- Systems Analysis & Design.
|
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TECHNOLOGY & ENGINEERING -- Electronics -- Circuits -- General.
|
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Ingénierie.
|
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Networks on a chip
|
| Form |
Electronic book
|
| Author |
Narayanan, Vijaykrishnan, 1972-
|
|
Das, Chita R.
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| ISBN |
9789048130313 |
|
904813031X |
|
