Title Reliability, availability and serviceability of networks-on-chip / by Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski

Published New York : Springer, ©2012

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Description 1 online resource (xiii, 209 pages) Contents Note continued: 3.6. On the Applicability of Standard SoC Test Strategies in NoC-Based Systems -- References -- 4. NoC Reuse for SoC Modular Testing -- 4.1. Basic NoC Reuse Model -- 4.1.1. Test Packets -- 4.1.2.Network Interface and Test Wrapper -- 4.1.3. Interface with External Tester -- 4.2. Preemptive Test Scheduling -- 4.2.1. Power-Aware Test Scheduling -- 4.3. Non-preemptive Test Scheduling -- 4.4. Multi-constrained Test Scheduling -- References -- 5. Advanced Approaches for NoC Reuse -- 5.1. Efficient Channel Utilization -- 5.2. Wrapper Design for NoC Reuse -- 5.3. ATE Wrapper for NoC Reuse -- 5.4. Test Scheduling for BE NoCs -- 5.4.1. Creating the Initial Solution -- 5.4.2. BottomUp Optimization -- 5.4.3. TopDown Optimization -- 5.4.4. Reshuffle Optimization -- 5.4.5. Implementation of the Defined Test Architecture -- 5.5. Discussion -- References -- 6. Test and Diagnosis of Routers -- 6.1. Introduction -- 6.2. Testing the Network Interfaces -- 6.3. Testing the Routers Note continued: 6.3.1. Structural-Based Strategies -- 6.3.2. Functional-Based Strategies -- 6.4.Comparing the Approaches -- 6.5. Concluding Remarks -- References -- 7. Test and Diagnosis of Communication Channels -- 7.1. Introduction -- 7.2. Testing the Communication Channels -- 7.2.1. Structural-Based Strategies -- 7.2.2. Functional-Based Strategies -- 7.3.Comparing the Approaches -- 7.4. Concluding Remarks -- References -- 8. Error Control Coding and Retransmission -- 8.1. Introduction -- 8.2. Joint Information and Time Redundancy -- 8.3. Joint Information, Time, and Space Redundancy -- 8.4. Joint Error Control Coding and Crosstalk Avoidance Codes -- 8.5.Comparing the Approaches -- 8.6. Discussion -- References -- 9. Error Location and Reconfiguration -- 9.1. Introduction -- 9.2. Fault Location -- 9.3. Reconfiguration -- 9.4.Comparing the Approaches -- 9.4.1. Fault Detection and Location Methods -- 9.4.2. Fault Reconfiguration Methods -- 9.5. Discussion and Directions for Future Work Note continued: References -- 10. Concluding Remarks -- 10.1.Networks-on-Chip, Testing, and Reliability as Key Challenges Towards Many-Core Systems -- 10.2.Network-on-Chip Testing -- 10.3. Testing Network-on-Chip Based Systems -- 10.4. Fault Tolerance for Network-on-Chip Based Systems -- 10.5.Network-on-Chip RAS in Emerging Technologies -- 10.6. Final Remarks -- References Summary Annotation This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures Analysis Engineering Computer aided design Systems engineering Circuits and Systems computertechnieken computer techniques computer software circuits Engineering (General) Techniek (algemeen) Bibliography Includes bibliographical references and index Notes English Subject Networks on a chip -- Reliability Networks on a chip -- Testing Integrated circuits -- Fault tolerance. COMPUTERS -- General. Ingénierie. Integrated circuits -- Fault tolerance Form Electronic book Author Morais Amory, Alexandre de. Soares Lubaszewski, Marcelo ISBN 9781461407911 1461407915 9786613353412 6613353418

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