| Description |
1 online resource |
| Series |
Springer series in advanced microelectronics, 1437-0387 ; [36] |
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Springer series in advanced microelectronics ; 36.
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| Contents |
1. Introduction -- Integrated D/A-Converters -- DACs for Highly Integrated Transceivers -- The Ideal D/A-Converter -- The Non Return-to-Zero DAC -- The Return-to-Zero DAC -- The Current-Steering DAC -- General Description -- Single-Polarity and Dual-Polarity Current Cells -- Passive and Active Output Stage -- Array Coding -- Unary Array -- Binary Array -- Segmented Array -- 2. Performance Figures of D/A-Converters -- Static Accuracy -- Gain and Offset Error -- Differential Nonlinearity -- Integral Nonlinearity -- Dynamic Performance. -- Harmonic Distortion -- Intermodulation Distortion -- Spurious Free Dynamic Range -- Dynamic Range -- Multitone Linearity -- Noise Performance -- Quantization "Noise" -- Circuit Noise -- Jitter Noise |
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3. Static Linearity -- Limitations for the Static Linearity -- Matching of Current Sources -- Statistical Description of the INL -- Statistical Description of the DNL -- Minimum Area Requirements -- Code-Dependent Output Impedance. -- Dynamic Element Matching Techniques -- Clocked Level Averaging -- Data-Weighted Averaging -- Other DEM Techniques -- Current Source Calibration -- Factory Trimming -- Self-calibration -- Local Calibration DAC -- Global Calibration DAC -- Trimmable Floating Current Source -- Dynamic Current Calibration -- 4. Dynamic Linearity -- Limitations for the Dynamic Linearity -- Frequency-DependentOutput Impedance -- A Generalized Switching Error Model -- Switching Transition Mismatch -- Charge Sharing at the Switching Node -- A SPICE-Simulation Example -- Other Nonlinear Effects -- Methods to Improve the Dynamic Performance -- Current Switch with Reduced Gate Voltage Swing -- Source Node Bootstrapping -- Source Node Isolation -- Differential Quad Switching -- Constant Digital Activity -- Return-to-Zero and Track/Attenuate. -- Double Return-to-Zero -- Full-Clock Interleaved Current Cells |
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5. Noiseshaped D/A-Converters -- A 14-bit Low-Power D/A-Converter -- Converter Architecture -- DEM Selection -- Unit Current Cell -- Low-Noise Biasing -- Output Stage -- Layout -- Experimental Results -- A 12-Bit/14-Bit Multistandard DAC -- Low-OSR Noiseshaper -- Interleaved Data Weighted Averaging -- Converter Architecture -- Current-Cell Design -- Low-Noise Biasing -- Output Stage Design -- Layout -- Experimental Results -- Literature Comparison of Noiseshaped DACs -- 6. Advanced Current Calibration -- A Self-calibrated 13-Bit 100-200MS/s D/A-Converter -- Converter Architecture -- Trimmable PMOS Current Cell -- Segmented Background Calibration -- Randomized Calibration Cycle -- Layout -- Experimental Results |
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A 13-Bit 130-300MS/s DAC with Active Output Stage -- Converter Architecture -- The Current Cells -- Direct Segment Calibration -- Programmable Biasing -- Push-Pull Operational Amplifier -- Output Stage Optimization -- Layout -- Experimental Results -- A Figure-of-Merit for Nyquist D/A-Converters -- 7. Conclusion and Outlook -- Conclusions -- Outlook -- A. DAC Bias Noise Model -- Bias Noise Model Without 1/f-Noise -- DMT Synthesis with Correlated 1/f-Noise -- Maximum SNR Limited by Correlated Bias Noise -- B. Jitter Noise -- Sampling Jitter Model -- Non Return-to-Zero DAC -- Return-to-Zero DAC -- Jitter in Multitone Systems -- C. Code-Dependent Output Resistance -- Single-Ended Converter -- Fully Differential Converter -- D. Switching errors -- Generalized Switching ErrorModel -- Switching Transition Mismatch with Thermometer Coding -- Switching Transition Mismatch with Data Weighted Averaging -- Charge Sharing with Thermometer Coding -- Charge Sharing with DataWeighted Averaging -- Output Voltage Feedthrough Factor -- Single-Polarity DAC with Passive Termination -- Dual-Polarity DAC with Active Termination -- Third-Order Two-Tone Nonlinearity |
| Summary |
This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested. With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area |
| Analysis |
Engineering |
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Electronics |
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Signal, Image and Speech Processing |
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Electronics and Microelectronics, Instrumentation |
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Semiconductors |
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Electronic Circuits and Devices |
| Bibliography |
Includes bibliographical references and index |
| Notes |
English |
| In |
Springer eBooks |
| Subject |
Digital-to-analog converters.
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Electronics.
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Electronics
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COMPUTERS -- Data Transmission Systems -- General.
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Ingénierie.
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Digital-to-analog converters
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| Form |
Electronic book
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| ISBN |
9783642312298 |
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3642312292 |
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