Table of Contents |
1. | Introduction: Multistate Devices and Logic | 1 |
1.1. | Resonant Tunneling Diode (RTD) | 2 |
1.2. | Resonant Tunneling Transistor (RTT) | 2 |
1.3. | Quantum Dot Gate Field-Effect Transistor (QDGFET) | 4 |
| References | 5 |
2. | Quantum Dot Gate Field-Effect Transistor: Device Structures | 7 |
2.1. | Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) | 7 |
2.2. | Scaling Issues | 7 |
2.3. | Quantum Dot | 11 |
2.4. | Quantum Dot Gate Field-Effect Transistor (QDGFET) | 11 |
2.4.1. | Device Structure | 11 |
| References | 18 |
3. | Quantum Dot Gate Field-Effect Transistors: Fabrication and Characterization | 21 |
3.1. | Fabrication Methodology | 21 |
3.1.1. | Ge0x-Cladded Ge Quantum Dots on Top of High-K Gate Dielectric | 21 |
3.1.2. | QDGFET: SiOx-Cladded Si Quantum Dots on Silicon-on-Insulator Substrate | 26 |
3.2. | Quantum Dot Gate Characterization | 27 |
3.2.1. | Atomic Force Microscopy (AFM) | 27 |
3.2.2. | Transmission Electron Microscopy (TEM) | 29 |
3.3. | ZnS Layer Characterization | 30 |
3.3.1. | X-Ray Diffraction | 30 |
3.4. | Cross-Sectional High-Resolution Transmission Electron Micrograph (HRTEM) | 31 |
3.5. | Electrical Characteristics | 33 |
3.5.1. | GeOx-Cladded Ge Dots on Top of ZnS-ZnMgS Gate Insulator | 33 |
3.5.2. | SiOx-Cladded Si Dots on Top of SiO2 Tunnel Insulator in SOI Substrate | 35 |
3.5.3. | Thin Layer of Silicon Nitride on Top of SiOx-Cladded Si Quantum Dots in the Gate Region of FET | 37 |
| References | 39 |
4. | Quantum Dot Gate Field-Effect Transistors: Theory and Device Modeling | 41 |
4.1. | Band Diagram of a MOSFET | 41 |
4.2. | Theory of Operations of a MOSFET | 42 |
4.2.1. | Accumulation | 42 |
4.2.2. | Strong Accumulation | 42 |
4.2.3. | Depletion | 43 |
4.2.4. | Weak Inversion | 44 |
4.2.5. | Strong Inversion | 44 |
4.3. | Band Diagram of a QDGFET | 45 |
4.4. | Theory of Operations of QDGFET | 46 |
4.4.1. | SiOx-Cladded Si Quantum Dots on SiO2 Gate Insulator | 46 |
4.4.2. | Ge0x-Cladded Ge Quantum Dots on ZnS-ZnMgS Gate Insulator | 49 |
4.4.3. | Thin Layer of SiN on Top of SiOx-Cladded Si Dots on Top of SiO2 Gate Insulator | 52 |
| References | 54 |
5. | Quantum Dot Gate NMOS Inverter | 55 |
5.1. | Introduction | 55 |
5.2. | Conventional NMOS Inverter | 55 |
5.3. | QDNMOS Inverter | 56 |
5.3.1. | Device Structure | 56 |
5.3.2. | Experimental Details for High-Resolution Transmission Electron Microscopy (HRTEM) | 56 |
5.3.3. | Fabrication Techniques | 58 |
| References | 63 |
6. | Quantum Dot Gate Field-Effect Transistor (QDGFET): Circuit Model and Ternary Logic Inverter | 65 |
6.1. | QDGFET Circuit Model | 65 |
6.2. | Inverter | 67 |
6.2.1. | The Static CMOS Inverter | 68 |
6.2.2. | Ratioed Logic: NMOS Inverter | 69 |
6.3. | Ternary Inversion Operation | 74 |
6.4. | Three-State Memory Cell | 77 |
| References | 80 |
7. | Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) Using Quantum Dot Gate Field-Effect Transistor (QDGFET) | 81 |
7.1. | Introduction | 81 |
7.2. | Analog-to-Digital (A/D) Conversion | 81 |
7.2.1. | Existing A/D Conversion Method | 82 |
7.2.2. | Variable Threshold Voltage Transistor | 87 |
7.2.3. | Comparator | 87 |
7.2.4. | QDGFET-Based Three-Bit Analog-to-Digital Converter (ADC) | 89 |
7.3. | Three-Bit Digital-to-Analog Converter (DAC) | 91 |
7.3.1. | Existing D/A Converter | 91 |
7.3.2. | D/A Converter: Flash Architecture | 94 |
7.4. | Noise Analysis | 95 |
7.5. | Six-Bit Analog-to-Digital Converter (ADC) | 97 |
7.5.1. | Comparator Design | 97 |
7.5.2. | ADC Architecture | 98 |
7.6. | Six-Bit Digital-to-Analog Converter (DAC) | 100 |
7.7. | Reconstruction Circuit | 100 |
7.8. | Noise Analysis | 102 |
| References | 103 |
8. | Performance in Sub-25-nm Range: Circuit Model, Ternary Logic Gates and ADC/DAC | 105 |
8.1. | QDGFET Circuit Model for Sub-25-nm Range | 105 |
8.2. | Scaling the Supply Voltage | 105 |
8.3. | Ternary Logic Inverter | 107 |
8.3.1. | Standard Ternary Logic Inverter (STI) | 107 |
8.3.2. | Negative Ternary Logic Inverter (NTI) and Positive Ternary Logic Inverter (PTI) | 108 |
8.4. | Two-Input Ternary Functions | 112 |
8.4.1. | Ternary Logic NAND | 113 |
8.4.2. | NAND as a Universal Logic Gate | 116 |
8.4.3. | Ternary Logic NOR | 118 |
8.4.4. | NOR as a Universal Logic Gate | 119 |
8.4.5. | Ternary Logic XOR Gate | 120 |
8.5. | Three-Bit Analog-to-Digital Converter (ADC) | 123 |
8.6. | Three-Bit Digital-to-Analog Converter (DAC) | 123 |
8.7. | Ternary Logic Decoder | 124 |
8.7.1. | First Kind | 124 |
8.7.2. | Second Kind | 125 |
| References | 126 |
9. | Conclusions | 127 |
9.1. | Conclusions | 127 |
| About the Author | 129 |
| Index | 131 |